The invention relates to chemical mechanical planarizing (CMP) formulations for removing barrier metals and, more particularly, to polishing compositions for selectively removing barrier metals in the presence of interconnect structures in integrated circuit devices.
In recent years, the semiconductor industry has increasingly relied upon copper electrical interconnects in forming integrated circuits. These copper interconnects have a low electrical resistivity and a high resistance to electromigration. Since copper is very soluble in many dielectric materials, such as silicon dioxide and low-K or doped versions of silicon dioxide, a diffusion barrier layer is necessary to prevent the diffusion of copper into the underlying dielectric material. Typical barrier materials include, tantalum, tantalum nitride, tantalum-silicon nitrides, titanium, titanium nitrides, titanium-silicon nitrides, titanium-titanium nitrides, titanium-tungsten, tungsten, tungsten nitrides and tungsten-silicon nitrides.
In response to increasing demands for high density integrated circuits, semiconductor producers now fabricate integrated circuits containing multiple overlying layers of metal interconnect structures. During device fabrication, planarizing each interconnect layer improves packing density, process uniformity, product quality and most importantly, enables manufacturing of multiple layer integrated circuits. Semiconductor producers rely upon chemical-mechanical-planarizing (CMP) as a cost effective means of producing flat substrate surfaces. The CMP process is typically carried out in a two-step sequence. First, the polishing process uses a “first-step” slurry specifically designed to rapidly remove copper. For example, Carpio et al., in “Initial Study on Copper CMP Slurry Chemistries” Thin Solid Films, 262 (1995), disclose the use on a 5 weight percent nitric acid solution for efficient copper removal.
After the initial copper removal, a “second-step” slurry removes the barrier material. Typically, second-step slurries require excellent selectivity to remove the barrier material without adversely impacting the physical structure or electrical properties of the interconnect structure.
Tunability of the copper and dielectric rates in the barrier polishing step is important. Because integration schemes used by different IC manufacturers vary; the rate selectivity required for the various films polished in the barrier CMP step also varies. Certain film stacks require higher copper and dielectric rates for topography correction; but on other occasions, low copper and dielectric rates reduce the total metal loss and reduce the interconnect resistance. In alkaline slurries, increasing oxidizer concentration increases the copper removal rate. Because copper forms protective oxide at alkaline pH levels, excessive copper corrosion is not a concern for these slurries. For acidic barrier slurries, this approach can cause copper corrosion problems even with excessive amounts of BTA added.
For example, Liu et al. in US Pat. Pub. No. 2004/0147118, disclose an acidic barrier slurry. This slurry provides the advantage of excellent barrier removal rate with low copper rate at acidic pH levels. In these slurries, the hydrogen peroxide level provides an effective toggle for controlling copper removal rate. Unfortunately, it has been discovered that pitting corrosion can occur when hydrogen peroxide levels become too high.
In view of the above, there exists a need to provide a second-step slurry that possesses a high removal rate of barrier materials, excellent selectivity to interconnect metals, controlled removal of dielectric materials with controlled copper removal rate without the detrimental effects of copper pitting corrosion.